1. Field of the Invention
This invention relates to semiconductor fabrication for a T-like transistor gate, and more particularly to a method for fabricating a field effect transistor (FET) gate with a T-like structure, in which the improved T-like structure has low resistance and can avoid damage to the gate oxide layer during an etching fabrication process.
2. Description of Related Art
FIG. 1 is a cross-sectional view of a conventional field effect transistor. In FIG. 1, a field effect transistor (FET) includes two interchangeable source/drain regions 14 formed in a semiconductor substrate 10 and a gate 12 formed over the substrate 10 between the interchangeable source/drain regions 14. There is a gate oxide layer 16 between the gate 12 and the substrate 10. The formation of the interchangeable source/drain regions 14 usually includes a thermal process for driving-in the implanted ions so that there is an overlap region 18 overlapping with the gate 12. This induces an undesired capacitor effect between the gate 12 and the interchangeable source/drain regions 14. The existence of the overlap region 18 causing an increase of capacitance results in a decrease of the operational speed of the FET and an increase of the power dissipation. Moreover, the existence of the overlap region 18 increases a probability that hot electrons can easily inject into the gate oxide layer 16 to reform the threshold voltage, which may affect the working voltage and FET performances.
A conventional technology, called lightly doped drain (LDD) technology, is proposed to solve hot electrons problems. The LDD structure has a lightly doped region to replace the overlap region 18 of FIG. 1. However, the LDD structure still has some problems of high series resistance and power dissipation. Another conventional method is proposed to form a FET with a T-like-structure gate, which is described below.
FIGS. 2A-2C are cross-sectional views of a semiconductor device schematically illustrating a conventional fabrication process for a FET with a T-like-structure gate. In FIG. 2A, an oxide layer 22, a polysilicon layer 24, and a metal layer 26 having a high melting point are sequentially formed over a semiconductor substrate 20, which is a P-type substrate. A photoresist layer 27 is formed on the metal layer 26 to define a region for the gate structure.
In FIG. 2B, using the photoresist layer 27 as an etching mask, a plasma etching process is performed to pattern the metal layer 26 and the polysilicon layer 24. Since the etching rate of the polysilicon layer 24 is three times faster than that of the metal layer 26, the polysilicon layer 24 is etched more. The remaining metal layer 26 and the remaining polysilicon layer 24 form together as a T-like gate of the FET, which is to be formed.
In FIG. 2B and FIG. 2C, after removing the photoresist layer 27 and the oxide layer 22 other than the region covered by the polysilicon 24, the remaining oxide layer 22 is a gate oxide layer of the FET. A process of implanting ions is performed to dope the exposed region of the substrate 20. Thus, two interchangeable source/drain regions 29 are formed in the substrate 20 on each side of the T-like gate 28. The FET is then accomplished. In this conventional example, the interchangeable source/drain regions 29 have no overlap region 18 of FIG. 1 with the T-like gate 28.
However, the FET shown in FIG. 2C still has several problems. For example, the resistance of the metal layer 26 increases because the width of the T-like gate 28 is reduced, and the plasma etching process used to form the T-like gate 28 may easily cause damage to the T-like gate 28. Moreover, because the formation of the T-like structure includes at least two deposition processes and makes use of a different etching rate between metal layer 26 and polysilicon layer 24, the fabrication complexity and uncertainty increase.